1. Field of the Invention
The invention relates to the field of output buffer circuits for outputting logic signals. It can be applied to any circuit producing logic signals, such as a memory. In a logic signal circuit, output buffer circuits are circuits generally placed between internal logic circuits and outputs or inputs/outputs of the logic signal circuit. They provide external circuits with logic signals produced by the internal circuits and match them to the electrical characteristics of the external circuits.
2. Description of the Prior Art
FIG. 1 is a summary illustration of an application of an output buffer circuit, in this case in a memory. This memory has an address input port 1 to receive addresses ADD of information to be read in the memory. These addresses are given to a decoding circuit 2 that produces the appropriate selection signals for reading, in a memory array 3, of pieces of information corresponding to the addresses received. A read circuit 4 enables the extraction of the desired information from the memory array. Information elements DATA.sub.-- OUT are provided at an output port 6 in the form of logic signals, through a buffer circuit 5a.
FIG. 2 illustrates a standard example of a buffer circuit 5a. It has two series-connected inverters 7 and 8. Inverter 7 receives the signals extracted by the read circuit 4, and inverter 8 provides these signals to the ports 6. The inverter 8 is made with relatively large-sized transistors so that they can have substantial current flowing through them. This precaution arises out of the fact that the output ports are typically linked to communication buses. These buses may be of great length, and a large number of circuits other than the memory may be connected to them. Consequently, the equivalent capacitance perceived by the memory at the port 6 is generally great. The greater the current given by the memory to the port 6, the shorter will be the time taken to charge this equivalent capacitance when the memory provides signals on the port. The function of the inverter 7 is to reverse the signal provided to the inverter 8 in such a way that the polarity of the signals received and provided by the buffer circuit are identical.
If the information elements take the form of sets of N logic signals, as is the case in parallel type memories, then of course a number N of buffer circuits are used.
One problem raised by this type of buffer circuit is its sensitivity to noise. Thus, the switching in the inverters 7 and 8 of the buffer circuit illustrated in FIG. 2 may induce a disturbance of the operation in the read circuit 4 giving the logic signals. Typically, the disturbances are due to the fact that the switching generates noise in the supplies during the state transitions. This noise takes the form of glitches in the supplies, by inductive or capacitive effect. Now, the read circuits generally use differential amplifiers. This makes them highly sensitive to variations in supply potentials. It is also possible to induce oscillation phenomena between the circuit 4 and the output of the circuit 5a.